Integrated circuit arrangements are produced with an ever greater packing density. This means that interconnects in metallizing layers have an ever shorter separation between them. In consequence, capacitances which are formed between the interconnects and lead to long signal delay times, to high power losses and to undesirable crosstalk, that is to say, which lead to an interaction between signals applied to adjacent interconnects, are increasing.
Silicon oxide is frequently used as a dielectric, as the isolation material between the interconnects, and its relative dielectric constant is ∈r=3.9.
So-called low-k materials, that is to say materials with a low ∈r value as the material for the intermetal dielectrics, are used in order to reduce the relative dielectric constant ∈r, and this leads to a reduction in the value of the coupling capacitances between interconnects embedded in an insulation material.
It is also known from the prior art, that cavities are produced between interconnects within an interconnect layer, in order to reduce the value of the relative dielectric constant, and thus the value of the coupling capacitance. The insulating dielectric which governs the capacitance between the interconnects has a relative dielectric constant ∈r which is approximately equal to unity in the area of the cavities. The interconnects themselves are surrounded by a material layer, composed of silicon oxide or a low-k material, in order to decouple them from the surrounding area.
The high coupling capacitances C between adjacent interconnects, which are becoming ever greater as circuits become increasingly miniaturized, are leading together with the resistance R of an interconnect to an RC switching delay for signals transported on the interconnects. This RC switching delay can be reduced using airgaps as an alternative to low-k materials, since the use of airgaps between interconnects, as the isolation material between metallization paths, considerably reduces the effective dielectric constant ∈r. By way of example, [1] to [4] disclose possible ways to provide airgaps.
In order to seal and to close a cavity between adjacent interconnects from the outside, a cavity or trench such as this in a layer arrangement can be sealed by the deposition of a covering layer, covering the trench. When sealing a trench-like cavity between interconnects, the aim is to deposit the material of such a covering layer well on the uppermost layer, but in contrast not to enter the trench and thus not to undesirably fill the cavity between adjacent interconnects with material, which would once again increase the relative dielectric constant ∈r between the interconnects.
Silicon oxide formed by ozone-activated decomposition of tetraethyl orthosilicate (TEOS) (so-called “ozone/TEOS”) is suitable as a material for a covering layer such as this, and can be deposited selectively well on silane-based silicon oxide as the material of the uppermost layer, but not in contrast on the silicon nitride as the material in the interior of the trench. Selective deposition means that the material to be deposited as the covering layer to close the cavity grows on silane-based silicon oxide, but in contrast does not grow, or grows at only a very slow rate, on silicon nitride.
Thus, according to the prior art, silicon nitride is frequently used as the material between airgap structures between interconnects, while in contrast a surface layer on which a covering layer is to be grown in a layer arrangement such as this is frequently formed from silane-based silicon oxide. However, this material configuration has the disadvantage that an RC switching delay which is excessive for many applications occurs, because of the high relative dielectric constant of silicon nitride (∈r=8).
[5] discloses a method for formation of a silicon oxynitride layer by means of a CVD method, using a plasma and a mixing gas, with the mixing gas containing an organic silane gas and a nitride gas on and between interconnects on a semiconductor chip. The silicon oxynitride layer has good edge coverage, according to the statements in [5].
Other methods for formation of a silicon oxynitride layer with good edge coverage are described in [6] and [7].
[8] describes the formation of a structure with airgaps between the interconnects. The layer formed with airgaps is, however, formed using SiH4, and thus using an inorganic silicon precursor material.
Another airgap structure is described in [9], in which case this structure is produced using only one “airgap layer” and, in order to increase the “aspect ratio” between the interconnects and thus in order to automatically form airgaps, a pad oxide layer, which is additionally applied to the interconnects.